Amorphous silicon thin film transistor is often used to manufacture thin-film transistor (TFT) display. However, such display has limited applications, due to low electron mobility (e.g., less than 1 cm2/V·S) and due to opaqueness and strong photosensitivity of the amorphous silicon in the visible light range. Compared with the emerging technologies such as organic light-emitting diode (OLED) display technology, transparent liquid crystal display (LCD) technology, and gate driver on array (GOA) glass technology, the thin-film semiconductor materials are desirable to provide higher electron mobility, better amorphous uniformity, and reduced threshold voltage (Vth) shift.
The metal oxide semiconductor thin film in the metal oxide semiconductor thin film transistor (Oxide TFT) may provide advantages including low deposition temperature, high electron mobility, and high visible light transmittance. In addition, the electron mobility of oxide TFT is less dependent on the particles size of the film, i.e., having a high homogeneity or uniformity on threshold voltage (Vth).
FIG. 1 is a schematic illustrating a conventional metal oxide thin film transistor array substrate. Such array substrate includes: a substrate 01 having a first indium tin oxide (ITO) layer (not shown in the sectional view of FIG. 1) formed on the substrate 01.
The array substrate in FIG. 1 also includes: a gate electrode 02 formed on the first ITO layer, a gate insulating layer 03 formed on the gate electrode 02, a metal oxide active layer 04 formed on the gate insulating layer 03, an etch stop layer (ESL) 05 along with source/drain electrodes 06 formed on the metal oxide active layer 04, a passivation layer 07 formed on the source/drain electrodes 06; and a second ITO layer (not shown in the sectional view of FIG. 1) formed on the passivation layer 07.
To form the above-described Oxide TFT array substrate in FIG. 1, a number of patterning processes may be used to sequentially form desired layers on the substrate 01. Each patterning process may include one or more processes including coating a photoresist layer, using a mask to expose the photoresist layer, developing the exposed photoresist layer, etching the desired layer under the photoresist layer, and removing the photoresist layer after etching. When forming the first ITO layer, the gate electrode, the active layer, the etch stop layer, the source/drain electrodes, the passivation layer, and the second ITO layer, various patterning processes may be performed using various different masks. Thus, when forming the Oxide TFT array substrate in FIG. 1, at least about seven times of patterning process are used and each patterning process must use a different mask. This increases manufacturing cost of the array substrate.
The disclosed thin film transistor devices, manufacturing methods, and display apparatus are directed to solve one or more problems set forth above and to solve other problems in the art.